SemiAnalysis’s 10,000-Word Deep Dive into CXMT: $50 Billion in Revenue and an IPO Amid a Super Cycle
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SemiAnalysis’s 10,000-Word Deep Dive into CXMT: $50 Billion in Revenue and an IPO Amid a Super Cycle
Deconstruct ChangXin’s technology roadmap, financial data, HBM challenges, and IPO structure.
Navigating Web3 tides with focused insightsAuthors: Ray Wang, Myron Xie, Dylan Patel, et al.
Translation & Compilation: TechFlow
TechFlow Introduction: CXMT (ChangXin Memory Technology) is poised to list on the STAR Market, potentially becoming the largest semiconductor IPO in Chinese history. Founded only in 2016, the company began by acquiring patents and talent from Qimonda—the bankrupt German DRAM manufacturer—and has since received nearly a decade of capital support from the Hefei municipal government, which tolerated sustained losses. CXMT achieved its first annual profit in 2025 and reported $7.3 billion in revenue for Q1 2026 alone. This 10,000-word research report by SemiAnalysis dissects CXMT’s technological roadmap, financial data, HBM challenges, and IPO structure—making it essential reading for understanding China’s position in the global memory chip industry.
The SemiAnalysis team first highlighted the massive memory demand driven by AI inference and agent-based workflows in its newsletter at the end of 2024. Since then, it has published multiple deep-dive reports on memory technologies and continuously tracked CXMT and China’s computing ecosystem. With CXMT expected to go public within the next few months, a dedicated in-depth analysis is timely and necessary. CXMT is likely to become China’s largest semiconductor IPO—and a milestone for this leading domestic memory manufacturer. From here onward, competition between CXMT and Samsung, SK hynix, and Micron will only intensify.
A Silicon Valley Returnee
CXMT’s founder Zhu Yiming graduated with a B.S. in Physics from Tsinghua University in 1994 and subsequently pursued graduate studies in Electrical Engineering at Stony Brook University, State University of New York. He spent many years working in Silicon Valley and around 2001 became the project lead at MoSys (Monolithic System Technology). In 2005, Zhu returned to China with a set of SRAM patents and $100,000 in seed funding to found GigaDevice, which later grew into one of the world’s top-tier NOR Flash suppliers. However, the global NOR Flash market is far smaller than DRAM or NAND Flash markets. Zhu’s ambitions were broader—he chose the DRAM赛道.
DRAM is not a game for fabless companies. It consumes enormous capital, faces formidable patent barriers, and depends critically on manufacturing capability. By 2016, only three players remained in the entire industry: Samsung, SK hynix, and Micron—fortified by four decades of accumulated patents and capital. Zhu’s SRAM patents and GigaDevice’s NOR Flash business could neither provide DRAM cell design nor DRAM process technology, nor could they circumvent the giants’ patent walls. Thus, when Zhu and the Hefei municipal government launched the DRAM project “Project 506” (which later became CXMT) in 2016, core technology had to be sourced externally.
That external source was a defunct German company.
The DRAM Foundation: The Qimonda Legacy
That defunct company was Qimonda. Qimonda filed for bankruptcy in January 2009 amid the global financial crisis and a subsequent memory market crash—but at the time, it was Europe’s leading DRAM manufacturer. As a spin-off from Infineon (itself tracing back to Siemens), Qimonda offered a rare alternative: a deep DRAM patent portfolio and a complete memory cell architecture—both developed outside the Samsung–SK hynix–Micron triad.
In June 2015, Polaris Innovations—a subsidiary of Canadian patent licensing firm WiLAN—acquired approximately 7,000 Qimonda patents and applications from Infineon for roughly €30 million. In December 2019, Polaris signed an agreement with CXMT, licensing a large batch of DRAM patents. CXMT executives have publicly stated that the company acquired approximately 2.8 TB of Qimonda technical documentation, forming the bedrock of CXMT’s DRAM business.
One key technology inherited and advanced by CXMT from Qimonda is the 46nm-class BWL (Buried Wordline) memory cell, which CXMT has pushed toward the 10nm node. BWL represents a core architectural innovation. Traditional designs place the access transistor gate along the wafer surface; BWL embeds the gate into a trench beneath the bitline. This delivers three benefits: shrinking the memory cell to a 6F² layout (vs. conventional 8F²), extending channel length without consuming surface area to suppress short-channel leakage (which affects data retention), and reducing gate–bitline parasitic capacitance. Buried wordlines combined with stacked capacitors constitute the architecture used today by all three major memory vendors. Qimonda—by persisting with the trench approach—had preserved precisely this stack/BWL technical reserve—and CXMT inherited exactly that.
Talent: From Frozen Blueprints to Living R&D Capability
Beyond patents, CXMT gained an even more enduring asset from Qimonda’s collapse: engineers. Qimonda operated a R&D center in Xi’an staffed by 400–500 engineers—one of its largest R&D outposts outside Germany. After Qimonda’s bankruptcy, although the entire Xi’an center was acquired by Tsinghua Unigroup, broader talent diffusion benefited CXMT.
CXMT also successfully recruited senior engineer Karl-Heinz Kuesters from Qimonda’s German headquarters. Kuesters served as VP of Technology and Pre-R&D at Siemens, Infineon, and Qimonda for 24 years. His pre-R&D pilot line focused on the stacked capacitor architecture—the very one CXMT ultimately adopted. He joined CXMT as a technical advisor, and EE Times dubbed him CXMT’s “ace card.” What Kuesters brought was tacit know-how—knowledge no patent or 2.8TB of documentation could capture: two decades of DRAM development experience enabling him to guide CXMT engineers on which Qimonda designs to retain, which to discard, and how to transition lab-proven memory cells into volume production. Such integration and yield judgment simply does not exist in any patent literature.
The U.S. side followed a similar pattern. Ping Er-xuan, CXMT’s VP for Future Technology Assessment—and the public architect of CXMT’s “46nm-to-10nm roadmap”—did not come from Qimonda but built his career at Micron, SanDisk, and Applied Materials, accumulating deep expertise in memory and materials technologies.
CXMT has also heavily recruited talent from Korea and Taiwan. Korean prosecutors reportedly charged former Samsung employees with technology leakage; dozens of Korean engineers are said to have worked at CXMT. A similar situation exists in Taiwan, where CXMT has persistently poached top-tier equipment and process engineers with generous compensation packages.
This is the key to understanding CXMT’s trajectory. Qimonda’s patents remain finite, expiring assets. What enables CXMT to advance from G4 to G5 and eventually to HBM is aggregated human capital—not documents: domestically trained engineers, Chinese engineers returning after careers at multinational firms, and a small number of foreign experts. Heritage was merely the starting point; talent transformed imported legacy into an engine for independent R&D. Yet this engine burned for nearly a decade before turning profitable. The question remains: who possesses the patience to keep fueling it?
State-Owned Venture Capital’s Patience
CXMT’s success cannot be divorced from strong support by local and central Chinese governments. The Hefei municipal government stands as a classic case study. Hefei is a national hub for technological innovation, having incubated several successful enterprises over the past two decades using its “patient state-owned venture capital” model: BOE (a global leader in display panels), NIO (a leading EV manufacturer), and now CXMT.
The Hefei municipal government did two critical things for CXMT.
First, it helped build a local supply chain around CXMT’s factory. Hefei’s strategy is to take large equity stakes in core “chain-leading” enterprises and then attract complementary upstream/downstream players. This model was applied to BOE in displays and to NIO in EVs—and replicated for CXMT beginning in 2016. Around CXMT’s facility in Hefei’s Airport Economic Zone, the government cultivated a dense local industrial cluster. Packaging and test facilities Peiton and Xinfeng sit literally adjacent to CXMT’s campus—Xinfeng derives over 99% of its revenue from CXMT. Guanggang’s on-site bulk gas plant supplies most of CXMT’s needs; Zhiwei Semiconductor—a subsidiary of Zhichun Technology—provides wafer recycling capacity in Hefei’s Xinzhan High-Tech Industrial Park. State-owned VC also directly controls Wenyi Technology, an upstream chip molding equipment supplier.
Second, Hefei’s state-owned VC was willing to sustain losses for a very long time. Unlike private equity funds obligated to deliver returns to LPs on fixed schedules, Hefei’s state-owned VC is backed ultimately by municipal and development zone SOEs—with no mandatory exit clock. It continued injecting capital into a company that didn’t achieve annual profitability until 2025 and accumulated approximately RMB 36.65 billion in net losses over nearly a decade. Project 506—launched in 2016—received about 80% of its initial funding (RMB 14.4 billion of RMB 18 billion) from Hefei’s state-owned capital. Although Hefei’s stake was diluted in subsequent rounds, it never sold down or exited. At IPO, the largest shareholder—Hefei Qinghui Integrated Circuit—holds 21.67%, and state-owned VCs collectively hold over 30%. The willingness to treat a fab as a ten-year bet rather than a fund-cycle return—that is the true catalyst enabling both technology and talent.
From Legacy to Autonomy
These three threads—patents, talent, and patient capital—make CXMT’s first decade clear. Qimonda provided the foundation: a licensed patent portfolio and memory cell architecture from outside the Samsung–SK hynix–Micron triad. Talent provided the drive: pivotal figures like Kuesters and Ping, combined with returning Chinese engineers from U.S. giants and controversial hires from Korea, transformed frozen blueprints into an evolving, scalable process. Then Hefei’s government supplied what the first two elements needed but couldn’t generate themselves: capital, patience, and localized supply chains. All three were indispensable.
We now turn to CXMT’s finances, technology, and equipment ecosystem.
The Next Step After Ten Years: IPO Amid a Super-Cycle
While CXMT’s first decade is impressive, it may merely be the opening chapter of a longer narrative. The company is preparing for one of China’s largest semiconductor IPOs in recent years—and possibly the most closely watched semiconductor listing globally in 2026. In December 2025, the Shanghai Stock Exchange formally accepted CXMT’s STAR Market listing application. Market rumors about its IPO preparations had persisted throughout 2024 and 2025. The latest update: CXMT submitted its registration application to the China Securities Regulatory Commission (CSRC) on May 27 and is currently undergoing final review.
CXMT’s IPO prospectus discloses substantial previously unavailable information. Combined with SemiAnalysis’s Memory Model, we can make more precise judgments about CXMT’s current standing and future trajectory.
At a high level, by virtually every metric, CXMT is already the world’s fourth-largest DRAM vendor—and widening its lead over second-tier memory vendors. In full-year 2025, CXMT’s revenue surged 156% to ~$8.6 billion (up from ~$3.3 billion in 2024 and ~$1.2 billion in 2023). Net profit turned positive for the first time, reaching $1 billion. Even so, CXMT’s 2025 DRAM revenue remains far below Samsung (~$72.3 billion), SK hynix (~$52.1 billion), and Micron (~$37.2 billion).
Caption: Global DRAM Vendor Revenue Comparison (Source: SemiAnalysis Memory Model)
In Q1 2026, CXMT reported $7.3 billion in revenue—a ~700% YoY increase—approaching its full-year 2025 revenue in a single quarter. Operating margin also expanded sharply to ~70%.
SemiAnalysis believes this is just the beginning. Based solely on disclosures in the prospectus, CXMT’s H1 2026 revenue is projected to grow sevenfold year-on-year, exceeding $16 billion. For full-year 2026, SemiAnalysis estimates CXMT’s revenue may surpass $50 billion. If realized, this would mean CXMT’s revenue has more than doubled annually since 2023—and its 2026 YoY growth exceeds 600%.
This explosive growth is driven less by technology or market share gains than by the cycle itself. Examining the data closely: in Q1 2026, CXMT’s bit shipment grew only 11%, while ASP (average selling price) rose ~57%. Prior quarters saw sequential ASP increases of 63% (Q3 2025) and 68% (Q4 2025). Performance was lifted overwhelmingly by surging prices—not by significant market share gains against peers. In bit terms, SemiAnalysis’s model shows CXMT’s market share rising from 9% in 2025 to 12% in 2027. A 3-percentage-point gain may seem modest—but in a market SemiAnalysis forecasts approaching $1 trillion by 2027, it’s enormous.
Caption: CXMT ASP vs. Bit Shipment Trends (Source: SemiAnalysis Memory Model)
Misconceptions About the “Chinese Memory Shock” Narrative
For readers unfamiliar with CXMT or the memory market, a more interesting finding is how CXMT’s pricing compares with industry leaders. Based on Memory Model data, CXMT’s DRAM ASP challenges a common misconception: that Chinese memory chips are structurally cheaper and thus threaten to disrupt the market and depress global prices. That may have held true in certain past cases—but not in this cycle.
Take Q1 2026 as an example: CXMT’s DRAM ASP is only ~5–10% lower than Samsung’s, SK hynix’s, and Micron’s. SemiAnalysis expects this gap to persist through 2026 but gradually widen—not due to intrinsic pricing differences, but because of product mix shifts. Leading vendors ship a higher proportion of server DRAM and HBM, whose pricing outlook outperforms consumer DRAM.
By end-2027, SemiAnalysis expects server DRAM and HBM to account for >50% of total DRAM end-market demand. Since server DRAM and HBM command higher per-GB pricing, leading vendors will further widen their ASP gap with CXMT—especially given anticipated sharp HBM price increases in 2027.
Caption: DRAM Vendor ASP Comparison (Source: SemiAnalysis Memory Model)
Profitability: A Gift of the Cycle
Strong ASP tailwinds significantly improved CXMT’s margins. Full-year 2025 gross margin reached 37.8%—close to Samsung’s 39.4% and Micron’s 39.8%, though far below SK hynix’s 60.4% (driven by higher HBM shipments). CXMT’s ~38% gross margin marks a huge leap from -113% in 2023 and -4.7% in 2024. 2025 wasn’t just CXMT’s highest-ever gross margin—it was the first year with positive gross profit.
Caption: DRAM Vendor Gross Margin Comparison (Source: SemiAnalysis Memory Model, Company Reports)
In 2026, margins improved further. Q1 operating margin hit 70%, compared to SK hynix’s 73%, Samsung’s 81%, and Micron’s 84%. Beyond ASP growth, CXMT’s margin improvement stems from its near-total focus on commodity DRAM—in the current environment, commodity DRAM’s margins actually exceed those of HBM. Per the prospectus, ~99% of CXMT’s 2025 bit shipments were traditional LPDDR and DDR products; HBM contributed negligibly to revenue and profit.
Caption: DRAM Vendor Operating Margin Comparison (Source: SemiAnalysis Memory Model, Company Reports)
A simple DDR5 unit-cost analysis clarifies the picture further. SemiAnalysis finds CXMT’s DDR5 cost per bit remains >30% higher than the big three. Yet with DDR5 pricing extremely robust in Q1 2026, CXMT’s gross margin still soared above 70%. This means CXMT’s margin improvement is primarily price-driven—not the result of substantive competitiveness or cost-structure improvements.
Caption: DDR5 Cost per Bit Comparison (Source: SemiAnalysis Memory Model)
Capacity Expansion: Closing in on Micron
Beyond record profits, CXMT is also catching up on capacity. By end-2026, SemiAnalysis projects CXMT will reach ~350,000 wafers/month, slightly below Micron’s ~385,000 wafers/month. By wafer capacity ranking, CXMT is poised to become the industry’s third-largest memory vendor.
Caption: Global DRAM Vendor Monthly Wafer Capacity Comparison (Source: SemiAnalysis Memory Model)
But CXMT still lags significantly behind the two giants: Samsung (~720,000 wafers/month) and SK hynix (~595,000 wafers/month). By 2027, with initial ramp-up at Shanghai Phase I and full utilization in Hefei and Beijing, CXMT’s capacity could reach ~420,000 wafers/month, representing ~17% of global DRAM capacity—up from ~13% in 2025. In bit terms, market share rises from 9% in 2025 to 12% in 2027.
By 2028, with full utilization in Hefei and continued ramp-up across both Shanghai phases, SemiAnalysis projects CXMT will reach 500,000 wafers/month—~17% of global DRAM supply.
Caption: CXMT Hefei Facility Capacity (Source: SemiAnalysis Memory Model)
Supply-Overhang Concerns: Not a Near-Term Risk
Given CXMT’s increasingly important role in global DRAM capacity, investors—as in every prior cycle—worry Chinese vendors might cause supply-demand imbalances. SemiAnalysis considers such concerns overblown for at least the next two years. Even after accounting for incremental capacity and bit shipments from CXMT and other memory vendors—and assuming utilization above 90%—DRAM supply remains extremely tight.
Caption: DRAM Supply-Demand Balance (Source: SemiAnalysis Memory Model)
Looking specifically at CXMT’s capacity ramp: ~85,000 / 70,000 / 80,000 wafers/month added annually in 2026–2028, versus Samsung’s 15,000 / 50,000 / 110,000, SK hynix’s 60,000 / 60,000 / 90,000, and Micron’s 30,000 / 90,000 / 115,000. Even including these additions, DRAM will remain in shortage by high-single-digit percentages in 2026—and the deficit will widen to low-to-mid double digits in 2027. SemiAnalysis has previously detailed why DRAM shortages may persist through 2028.
CXMT lacks the ability—or incentive—to irrationaly accelerate capacity expansion beyond its current pace to disrupt the market, because fab construction cycles are too long. The current highly favorable pricing environment is precisely what drives CXMT’s explosive performance—and CXMT naturally hopes this environment persists. SemiAnalysis’s tracking of fab construction progress shows no signs of such acceleration, though it bears noting that Shanghai’s full-capacity output could exceed 400,000 wafers/month.
HBM: CXMT’s Dilemma
On HBM, CXMT allocates very limited wafer capacity. As of end-2025, only ~5,000 of CXMT’s ~2.65 million wafers/month were allocated to HBM. SemiAnalysis projects this to rise to ~30,000 wafers/month by end-2026 and ~55,000 by end-2027—consistent with the prospectus disclosure that ~99% of 2025 revenue came from DDR and LPDDR.
Caption: CXMT HBM Wafer Capacity Allocation (Source: SemiAnalysis Memory Model)
Yet this allocation could change. China’s push for AI compute autonomy may conflict with CXMT’s commercial priorities—and that pressure is expected to strengthen over time. SemiAnalysis incorporates government guidance pushing CXMT toward HBM capacity reallocation in its forecast, projecting accelerated HBM expansion in 2027 and 2028. CXMT’s HBM capacity is projected to reach 55,000 wafers/month in 2027 and 100,000 wafers/month in 2028, increasing its share of global HBM wafer supply from 1% in 2025 to 12% in 2028.
It must be remembered that CXMT differs from other memory vendors: it is not merely an economically and technologically important company, but also a strategic national asset leveraged to advance policy priorities.
From a short-term commercial logic standpoint, prioritizing commodity DRAM over HBM is rational for CXMT. Commodity DRAM currently delivers significantly higher margins than CXMT’s HBM products, and bit output per wafer area is over three times higher for commodity DRAM than for HBM. At this stage—where HBM technology remains immature—large-scale HBM capacity investment would consume scarce wafer capacity better deployed toward higher-margin, higher-volume commodity DRAM. Yet China must advance its HBM efforts, because U.S. export controls strictly restrict HBM sales to China, and Korean vendors’ shipments to China rely only on narrow loopholes.
HBM Technology Gap
In terms of technology readiness, SemiAnalysis believes CXMT is still struggling to stabilize mass production of HBM3 8-hi, with 12-hi posing even greater challenges.
On the front-end, CXMT has made progress on production stability at its **G4 (equivalent to 1z-node)** process, with most DRAM output in 2026 based on G4. But DRAM die for HBM—due to larger die size and stricter performance requirements—exhibits significantly lower front-end wafer-sort yield than commodity DRAM. SemiAnalysis views front-end yield as CXMT’s major challenge, with a substantial gap remaining versus peers. Though G4 yield has improved, low profitability in 2024 and 2025 suggests it may still fall below the industry’s mature 1z-node standard of 85–90% yield—indicating ongoing constraints from equipment limitations and manufacturing experience.
Caption: CXMT DRAM Process Node Roadmap & Yield (Source: SemiAnalysis Memory Model)
The next-generation G5 node (equivalent to 1a-node) could theoretically advance without EUV lithography—like Micron’s 1a—but faces escalating manufacturing and design challenges. These challenges intensify further when applying the node to HBM DRAM die.
Die stacking is CXMT’s biggest HBM hurdle. HBM stacking introduces severe technical difficulties: thermal stress, die cracking, warpage, bonding defects, and yield loss across multi-layer stacks. These issues worsen when progressing from HBM3 8-hi to HBM3 12-hi and beyond to HBM3E—particularly because CXMT lacks manufacturing experience at 12-hi and above.
Stacking challenges are not unique to CXMT. Leading vendors face die cracking, thermal management, and yield loss issues even on 12-hi HBM4. 16-hi and 20-hi are even more difficult—Rubin Ultra’s decision to adopt 12-hi HBM4E instead of 16-hi stems partly from supply constraints: 16-hi requires more DRAM wafers, is harder to manufacture, incurs higher wafer loss, and yields fewer effective bits.
SemiAnalysis believes CXMT is increasingly likely to skip HBM3 entirely and focus directly on HBM3E 8-hi and 12-hi—for two reasons: first, customers need more competitive HBM products by the 2027 timeframe; second, mainstream accelerators will then feature HBM3E, HBM4, and HBM4E.
Caption: Global HBM Roadmap Comparison (Source: SemiAnalysis Memory Model)
On the back-end packaging front, whether CXMT uses MR-MUF or TC-NCF remains debatable—but packaging challenges are relatively more manageable, as CXMT and its OSAT partners face fewer restrictions under export controls. CXMT has collaborated closely with top-tier OSATs like Tongfu Microelectronics, and back-end capability should be gradually improving—though gaps remain versus leading memory vendors.
Based on existing manufacturing challenges, SemiAnalysis models front-end and back-end yields for CXMT’s HBM3 8-hi at ~35% and ~70%, respectively—resulting in an overall yield of only ~25%. For HBM3 12-hi or HBM3E 12-hi—given higher stacking and bonding difficulty—overall yield would be even lower. At such yield levels, CXMT’s HBM output per wafer is far below leading vendors’. More critically, HBM profitability is extremely low—especially relative to commodity DRAM in the current pricing environment.
CXMT’s HBM dilemma is also reflected in product adoption. SemiAnalysis believes only Huawei, Cambricon, and a few emerging Chinese AI chip startups may adopt CXMT’s HBM—though adoption rates among them could be high. Domestic AI accelerator vendors still prefer foreign HBM3—or even HBM3E—whenever possible, whether via any available channels or inventory stockpiled before the December 2024 export controls. As domestic cloud providers rapidly expand capex and compute infrastructure, demand for domestic HBM is also growing quickly.
A notable exception: Huawei and CXMT will co-develop custom HBM not based on JEDEC standards or PHY—helping offset bandwidth disadvantages.
China’s HBM supply constraints may be more severe than implied by the slow pace of domestic HBM development. The three major HBM suppliers themselves face tight supply—and per the December 2024 U.S. export controls, they are restricted from selling HBM2E and newer generations to China. In a supply-constrained environment, their willingness to risk violations for Chinese sales is even lower.
Yet gray-market re-export and smuggling complicate the picture further. SemiAnalysis understands some Chinese firms continue acquiring HBM3 via various channels. Re-export through overseas offices or third-country partners remains one path; some third-country OSATs or intermediaries also facilitate such flows. Certain entities export partially assembled systems or modules (not classified as finished GPUs or ASICs—and thus still permitted for export to China), after which HBM is de-soldered and re-packaged onto domestic GPUs or ASICs.
What the IPO Structure Reveals
CXMT may become one of China’s largest semiconductor IPOs—and its equity structure warrants closer attention than its headline financials. CXMT reported consolidated net profit of RMB 7.14 billion in 2025, yet attributable net profit to parent shareholders was only RMB 1.87 billion—74% belonging to minority interests.
The reason lies in its equity structure. CXMT holds only 30.68% economic interest in Changxin Xinqiao and 31.72% in Changxin Jidian Beijing—but exercises 73.01% and 75.32% voting control, respectively, via long-term concerted action agreements. This allows CXMT to consolidate fabs it effectively does not own—overstating publicly available profit by roughly fourfold.
Caption: CXMT Consolidated Profit vs. Attributable Profit (Source: SemiAnalysis Memory Model, Company Reports)
The same voting structure undermines CXMT’s claim of “no controlling shareholder, no actual controller” (listed formally as a governance risk in the prospectus). Through concerted action agreements, CXMT exercises majority voting control over fabs—while the National Integrated Circuit Industry Investment Fund Phase II, plus Hefei and Anhui SOEs, collectively hold well over 30% post-IPO. This arrangement appears designed to manage export-control scrutiny and foreign investor perceptions—at a time when CXMT’s ties to the Chinese government face maximum scrutiny.
Caption: CXMT Equity Structure (Source: SemiAnalysis Memory Model, Company Reports)
Valuation: An Undervalued Floor
CXMT plans to raise RMB 29.5 billion (~$4.1 billion), representing 10–15% of its post-IPO fully diluted share count. Raising the full amount via IPO implies: ~RMB 4.41/share at 10% dilution, ~RMB 2.78/share at 15% dilution (vs. RMB 2.63/share in the June 2025 financing round). The lower end offers virtually no premium over the prior round—even though Q1 2026 delivered $7.3 billion in revenue and $4.8 billion in net profit. RMB 2.78/share implies a valuation of ~RMB 197 billion (~$27 billion)—just 1.8x annualized attributable net profit for H1 2026. SemiAnalysis believes this floor valuation is too low; the actual pricing should be significantly higher.
Caption: CXMT IPO Valuation Analysis (Source: SemiAnalysis Memory Model, Company Reports)
Fund Use: Focus on Commodity DRAM, No Mention of HBM
The RMB 29.5 billion fund use reinforces CXMT’s current priorities. Of this, RMB 20.5 billion (69.5%) goes to wafer fab expansion and DRAM technology upgrades; RMB 9 billion (30.5%) funds forward-looking DRAM R&D. The prospectus discloses no dedicated HBM projects—and does not mention HBM at all. Project descriptions emphasize newer process platforms, product iteration, and migration of existing lines toward mid-to-high-end DRAM. The IPO’s core purpose is strengthening CXMT’s DRAM manufacturing and technology foundation—with no public funding commitment to near-term HBM expansion.
Caption: CXMT IPO Fund Allocation (Source: SemiAnalysis Memory Model, Company Reports)
A Cyclical Timing Warning
The magnitude of profit swings warrants a cautionary note on cyclical timing. In its December 2025 prospectus, CXMT projected full-year 2025 attributable net loss of RMB 0.6–1.6 billion. Five months later, the updated prospectus reported RMB 1.87 billion in profit—more than double the prior upper estimate for consolidated profit. This illustrates how quickly peak DRAM pricing can shift valuation denominators—in either direction.
Alibaba’s Dual Role
One final detail: Alibaba’s presence on CXMT’s shareholder list changes how we interpret CXMT’s demand-side dynamics. Alibaba Cloud serves both as a core hyperscale customer and as a ~4% shareholder and endorser—ranking alongside Zhu Yiming’s GigaDevice (~1.8%). Domestic demand volume is thus somewhat secured—a competitive advantage Korean giants lack in their home markets. Though the percentage is small, its significance is far greater.
Note: The latter half of this article—including deep analysis of CXMT’s equipment ecosystem, export-control impacts, and China’s memory and compute ambitions—is SemiAnalysis’s paid content and is not included in this translation.
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